`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:11:15 03/21/2011 
// Design Name: 
// Module Name:    el 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module pel #(
  parameter       SIMULATION = "FALSE",
  parameter       LANES = 4
)(
  input           SYS_CLKp,
  input           SYS_CLKn,
  input           SYS_RST,
  
  input           UART_RX,
  output          UART_TX,
  
  output  [0:0]   DDR3_CLKp,
  output  [0:0]   DDR3_CLKn,
  output  [0:0]   DDR3_CKE,
  output  [12:0]  DDR3_A,
  output  [2:0]   DDR3_BA,
  output          DDR3_CASn,
  output          DDR3_RASn,
  output          DDR3_WEn,
  output  [0:0]   DDR3_CSn,
  inout   [63:0]  DDR3_DQ,
  inout   [7:0]   DDR3_DQSp,
  inout   [7:0]   DDR3_DQSn,
  output  [7:0]   DDR3_DM,
  output  [0:0]   DDR3_ODT,
  output          DDR3_RSTn,
  
  input           ETHERNET_MII_TX_CLK,
  output  [7:0]   ETHERNET_TXD,
  output          ETHERNET_TX_EN,
  output          ETHERNET_TX_ER,
  output          ETHERNET_TX_CLK,
  input   [7:0]   ETHERNET_RXD,
  input           ETHERNET_RX_DV,
  input           ETHERNET_RX_ER,
  input           ETHERNET_RX_CLK,
  output          ETHERNET_MDC,
  inout           ETHERNET_MDIO,
  output          ETHERNET_RSTn,
  
  output  [23:0]  FLASH_A,
  inout   [15:0]  FLASH_DQ,
  output          FLASH_WEn,
  output          FLASH_OEn,
  output          FLASH_CEn,
  
  output  [7:0]   LED,
  input   [7:0]   DIP,
  output          LED_C,
  output          LED_W,
  output          LED_S,
  output          LED_E,
  output          LED_N,

  inout   [6:0]   LCD_GPIO,

  input           PCIE_REFCLKp,
  input           PCIE_REFCLKn,
  input           PCIE_PERSTn,
  
  input   [3:0]   PCIE_RXP,
  input   [3:0]   PCIE_RXN,
  output  [3:0]   PCIE_TXP,
  output  [3:0]   PCIE_TXN
  );


  wire sys_clk;
  wire pcie_clk;
  IBUFGDS IBUFGDS_sys_clk (.O(sys_clk), .I(SYS_CLKp), .IB(SYS_CLKn));
  IBUFDS_GTXE1 IBUFDS_GTXE1_pcie_clk (.O(pcie_clk), .I(PCIE_REFCLKp), .IB(PCIE_REFCLKn));

  wire locked;
  wire ddr_init_done;
  
  eps eps(
  .SYS_CLK          (sys_clk),
  .SYS_RST          (SYS_RST),
  
  .UART_RX          (UART_RX),
  .UART_TX          (UART_TX),
  
  .DDR_CLKp         (DDR3_CLKp),
  .DDR_CLKn         (DDR3_CLKn),
  .DDR_CKE          (DDR3_CKE),
  .DDR_A            (DDR3_A),
  .DDR_BA           (DDR3_BA),
  .DDR_CASn         (DDR3_CASn),
  .DDR_RASn         (DDR3_RASn),
  .DDR_WEn          (DDR3_WEn),
  .DDR_CSn          (DDR3_CSn),
  .DDR_DQ           (DDR3_DQ),
  .DDR_DQSp         (DDR3_DQSp),
  .DDR_DQSn         (DDR3_DQSn),
  .DDR_DM           (DDR3_DM),
  .DDR_ODT          (DDR3_ODT),
  .DDR_RSTn         (DDR3_RSTn),
  
  .ETHERNET_MII_TX_CLK(ETHERNET_MII_TX_CLK),
  .ETHERNET_TXD     (ETHERNET_TXD),
  .ETHERNET_TX_EN   (ETHERNET_TX_EN),
  .ETHERNET_TX_ER   (ETHERNET_TX_ER),
  .ETHERNET_TX_CLK  (ETHERNET_TX_CLK),
  .ETHERNET_RXD     (ETHERNET_RXD),
  .ETHERNET_RX_DV   (ETHERNET_RX_DV),
  .ETHERNET_RX_ER   (ETHERNET_RX_ER),
  .ETHERNET_RX_CLK  (ETHERNET_RX_CLK),
  .ETHERNET_MDC     (ETHERNET_MDC),
  .ETHERNET_MDIO    (ETHERNET_MDIO),
  .ETHERNET_RSTn    (ETHERNET_RSTn),
  
  .FLASH_A          (FLASH_A),
  .FLASH_DQ         (FLASH_DQ),
  .FLASH_WEn        (FLASH_WEn),
  .FLASH_OEn        (FLASH_OEn),
  .FLASH_CEn        (FLASH_CEn),
  
  .LOCKED           (locked),
  .DDR_INIT_DONE    (ddr_init_done),
  
  .LCD_GPIO         (LCD_GPIO),

  .PCIE_REFCLK      (pcie_clk),
  .PCIE_PERSTn      (PCIE_PERSTn),
  .PCIE_RXP         (PCIE_RXP),
  .PCIE_RXN         (PCIE_RXN),
  .PCIE_TXP         (PCIE_TXP),
  .PCIE_TXN         (PCIE_TXN)
  );
  
  assign LED = DIP;
  assign LED_E = ddr_init_done;
  assign LED_C = locked;
  assign LED_N = 1'b0;
  assign LED_S = 1'b0;
  assign LED_W = 1'b0;
endmodule
